Behavioral Analysis of Different ALU Architectures

Digital design is an amazing and very broad field. The applications of digital design are present in our daily life, including Computers, calculators, video cameras etc. In fact, there will be always need for high speed and low power digital products which makes digital design a future growing business. Low power and high speed is challenging work in processor design. Implementing power optimization on all components of the processor is a choice. One of the most basicoperational units in theprocessor is an (Arithmetic logic unit) ALU. ALU is a critical component of a microprocessor and is the core component of central processing unit. Furthermore, it is the heart of the instruction execution portion of every computer. It has the capability of performing a number of Arithmetic and logical operations such as addition, subtraction, complement, bit shifts and magnitude comparisons. Hence the speed, circuit delay, layout density, and power consumption trade-off is important for the portable digital system designers. This paper proposed to design and compare different parameters like low power, number of transistors and high speed of ALU’s .It compares the conventional CMOS ALU with Pseudo NMOS logic and MOS Logics. These different circuit parameters are compared with TANNER 13.1 using IBM SCN CMOS 65nm technology at room temperature. Results of comparison are shows that the Pseudo NMOS logic requires a lower number of transistors and performs well in terms of delay other than remaining architectures.